The present invention relates generally to nonvolatile semiconductor memory devices, and more particularly, to an electrically erasable and programmable read only memory (EEPROM) device having a page program mode and which is characterized by a unique architecture which provides a higher level of integration density than is possible with currently available EEPROMs having a page program mode.
Various methods have been heretofore proposed for improving the operating speed of nonvolatile semiconductor memory devices such as EEPROMs, flash EEPROMs, and the like. One of these methods, commonly referred to as a page program mode, is performed by temporarily storing data in a data buffer and simultaneously writing the data in a selected column of the memory array, thereby minimizing the time for programming data into the memory device.
Known techniques for implementing the page program mode are disclosed, for example, in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 24, No. 5, October 1988, pp. 1238-1243 and IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 5, October 1988, pp. 1164-170. With these known techniques, a data storing circuit for storing data and a program voltage generating circuit for generating a program voltage are connected to every bit line. Because these techniques require that the data storing circuit and the program voltage generating circuit be connected to every bit line, there is an inherent limitation on the size of the memory cells or the width between bit lines, thereby limiting the level of integration density of the semiconductor memory device.
Based upon the above and foregoing, it can be appreciated that there presently exists a need in the art for a nonvolatile semiconductor memory device having a page program mode which overcomes the above-described limitation and shortcoming of the presently available nonvolatile semiconductor memory devices having a page program mode.